Fast growth of the pervasive computing and handheld/communication industry has generated exploding demand for high capacity nonvolatile solid-state data storage devices. Current technology like flash memory has several drawbacks such as slow access speed, limited endurance, and the integration difficulty. Flash memory (NAND or NOR) also faces significant scaling problems.
Resistive sense memories are promising candidates for future nonvolatile and universal memory by storing data bits as either a high or low resistance state. One such memory, MRAM, features non-volatility, fast writing/reading speed, almost unlimited programming endurance and zero standby power. The basic component of MRAM is a magnetic tunneling junction (MTJ). MRAM switches the MTJ resistance by using a current induced magnetic field to switch the magnetization of MTJ. As the MTJ size shrinks, the switching magnetic field amplitude increases and the switching variation becomes more severe. Resistive RAM (RRAM) is another resistive sense memory that has a variable resistance layer that can switch between a high resistance state and a low resistance state (for example by the presence or absence of a conductive filament) by applicant of a current or voltage.
Spin polarization current induced magnetization switching has been introduced to the MRAM design. Spin-Transfer Torque RAM (STRAM), uses a (bidirectional) current through the MTJ to realize the resistance switching. The switching mechanism of STRAM is constrained locally and STRAM is believed to have a better scaling property than the conventional MRAM.
However, a number of yield-limiting factors must be overcome before STRAM enters the production stage. One concern is that it can be difficult to reliably read the STRAM from cycle to cycle and from bit to bit in a memory array. One read technique to sense the state of an STRAM bit is to inject a small current through the bit and measure the voltage at the end of a bit line, then compare it with a reference voltage, Vref. Ideally, one would like to have Vref situated at a voltage value midpoint between the Vhigh and Vlow distributions. However, due to fabrication process variation of the memory array, the electrical property value of each memory cell in the memory array can deviate from the designed value.